To produce a MOSFET as one type of MOS type semiconductor device, a p base region is formed by diffusing impurities into a selected area of a surface layer of an n type semiconductor substrate such that a pn junction appears on the surface of the substrate, and an n source region is formed in a surface layer of the p base region in a similar manner. A gate electrode is then formed on an insulating film, over the surface of a channel region provided by a surface layer of the p base region that is interposed between the n source region and the n type semiconductor substrate. Also, a source electrode is formed in contact with both the p base region and the n source region, and a drain electrode is formed on the other surface of the n type semiconductor substrate. By applying a suitable voltage to the gate electrode, an inversion layer appears in the channel region, to reduce resistance between the drain electrode and the source electrode, so that current flows between the drain electrode and the source electrode through the inversion layer.
To produce IGBT as another type of MOS type semiconductor device, an additional p type region is formed on the side of the drain electrode of the MOSFET. With the p type region thus added, the IGBT is capable of modulating the conductivity, utilizing injection of minority carriers.
The MOS type semiconductor devices as described above have been widely used in switching circuits because the devices provide low ON-state resistance and high switching speed, and can be easily controlled by changing voltage applied thereto.
In recent years, MOS type semiconductor devices used as switching elements in switching currents are more likely to receive surge voltage generated in the circuits, because of simplification of the circuits from which snubbers are eliminated, and reduction in the size of the semiconductor devices. When such a MOS type semiconductor device operates to stop current flow from an inductive load, for example, the voltage applied to the semiconductor device increases due to energy stored in an inductor, and may become even higher than the power supply voltage in some cases. The resulting overvoltage stress may cause breakdown of the MOS type semiconductor device. Thus, the semiconductor device used as a switching element has been desired to have an increased breakdown voltage or higher capability to withstand avalanche breakdown.
In the meantime, as a new trend of the MOS type semiconductor device, so-called intelligent devices, in other words, MOS type semiconductor apparatuses including MOS type semiconductor devices, have been used in these days. In this type of apparatus, the semiconductor device is integrated with a circuit that senses overcurrent, temperature, or the like, and feeds detection signals back to the gate. In such a MOS type semiconductor apparatus, it is particularly important to protect its gate and control input terminal against surge voltage.
FIG. 14 is a circuit diagram showing an equivalent circuit of a MOS type semiconductor apparatus provided with an arrangement for protecting the gate.
In this apparatus, a Zener diode 5 is connected between the source S and the gate G of a main MOS type semiconductor device 2. The Zener diode 5 functions to protect the device by bypassing current when overvolgate or excess voltage is applied to the gate G. A resistance 6 functions to prevent high-voltage noise from being applied to the gate G due to disconnection of a gate lead, for example. Between the drain D and the gate G is connected a series Zener diode array 3 in which a large number of pairs of Zener diodes are connected in series such that each pair of diodes are formed back to back. If the voltage applied to the drain D becomes higher than the clamp voltage of the series Zener diode array 3, a difference between the drain voltage and the clamp voltage is applied to the gate G, so as to turn on the main MOS type semiconductor device 2, thereby protecting the device from the overvoltage.
The series Zener diode array 3 connected between the drain D and the gate G is formed using polycrystalline silicon or polysilicon that is deposited on an insulating film over a semiconductor substrate of the MOS type semiconductor apparatus, as disclosed in U.S. Pat. No. 5,365,099.
The inventors of the present invention fabricated an intelligent IGBT that includes a Zener diode between the gate G and the source S for protecting the device against surge voltage, a means for detecting overcurrent, or the like, and an IGBT as a MOS type semiconductor device that provides the output stage. FIG. 15 shows an equivalent circuit of the intelligent IGBT. The gate G of the semiconductor apparatus is connected to a gate (g) of a main IGBT 4 as the output stage, via an internal control circuit 9 for sensing and computing. A Zener diode 5 connected between the gate G and the source S serves to protect the device against surge voltage. When an overvoltage is applied to the gate G, the Zener diode 5 performs a bypassing functions so as to protect the device against the overvoltage. A series Zener diode array 3 having a large number of pairs of Zener diodes is connected between the drain D and the gate g of the main IGBT. Each pair of the Zener diodes are formed back to back, namely, the anodes of each pair of the diodes are connected to each other, and adjacent pairs are connected with corresponding cathodes facing with each other. If a high voltage applied to the drain D becomes higher than the clamp voltage of the series Zener diode array 3, a difference between the drain voltage and the clamp voltage is applied to the gate g of the main IGBT 4, to turn on the main IGBT 4, thereby protecting the device from the overvoltage. A power supply of the internal control circuit 9 is taken from the control input terminal G. In the circuit of FIG. 15, the power supply terminal V.sub.DD is directly connected to the control input terminal G. The Zener diode 5 and the series Zener diode array 3 are formed by depositing polysilicon on an insulating film over the semiconductor device.
A surge voltage test was conducted on the device thus fabricated. FIG. 16(a) shows a test circuit, and FIG. 16(b) shows waveforms obtained in the test.
After a switch s1 was closed and a capacitor C was charged by a power supply Vcc, the switch s1 was opened. Then, a switch s2 was closed, and a test voltage was applied to a test device (DUT). The capacitance C was 33 .mu.F, and resistances Ra and Rb were 100.OMEGA. and 75 .OMEGA., respectively, while the power supply voltage was varied in the range of 30 to 500 V.
As shown in FIG. 16(b), the waveform of the voltage applied to the test device takes the form of a pulse having a width of about 9 ms, which rapidly rises in the initial period, and then gradually decreases.
In the surge voltage test, if the test voltage was increased to be larger than 100V, some test devices broke down. In many cases, the breakdown occurred at around the Zener diode 5.
The semiconductor apparatus as described above has another problem. To integrate the internal control circuit with the IGBT, the known apparatus employs an isolation structure using an embedded layer as reported by Wrathall, R. S. et al. in Proc. of the Symposium on High Voltage and Smart Power Devices, p.384, (1989), or an SOI isolation structure in which the control circuit is isolated by means of the substrate of the IGBT and an oxide film, for example. These methods, however, requires complicated and numerous process steps, which result in increased cost. In the production of the IGBT as described above, the inventors did not use these methods, but employed a self isolation structure as the simplest one that shortens the fabrication process, when integrating the internal control circuit with the IGBT.
FIG. 17 is a cross-sectional view showing an internal control circuit portion integrated on the MOS type semiconductor apparatus. This portion includes an p.sup.+ drain layer 21, n.sup.+ buffer layer 22, n drift layer 23, and a drain electrode 30, which are shared by the IGBT portion of the output stage. A p.sup.- well 34 is formed in a surface layer of the n drift layer 23, and an enhancement-type n channel MOSFET 51 and a depletion-type n channel MOSFET 61 are formed in and above a surface layer of the p.sup.- well 34. More specifically, n.sup.+ drain regions 53, 63 are formed in the surface layer of the p.sup.- well 34, and drain electrodes 60, 70 are formed in contact with the surfaces of the n.sup.+ drain regions 53, 63, respectively. Also, n.sup.+ source regions 56, 66 are formed in the surface layer of the p.sup.- well 34, and source electrodes 59, 69 are formed in contact with the surfaces of the n.sup.+ source regions 56, 66. Reference numeral 64 denotes an n channel doped region for controlling the threshold voltage, and 58 and 68 denote gate electrode layers. The drain electrode 70 of the depletion-type n channel MOSFET 61 is connected to the power supply terminal (V.sub.DD in FIG. 15) of the internal control circuit.
In the self isolation structure as described above, the p.sup.+ drain layer 21, n.sup.+ buffer layer 22, n drift layer 23, p.sup.- well 34, and the n.sup.+ drain region 63 provides a pnpn four-layer structure. Namely, this structure involves a parasitic thyristor consisting of these four layers. The parasitic thyristor of the internal control circuit portion is forward-biased during the operation of the intelligent IGBT, or when a surge voltage is applied to make the control input terminal (G) negative with respect to the output terminal (S). The parasitic thyristor, when it is forward-biased, latches up as indicated by the arrow 71 in FIG. 17, and may result in breakdown of the device.